A comparator implemented on an integrated circuit can perform a variety of useful functions. A comparator senses two input voltages and generates an output signal that indicates which of the two input voltages has a greater magnitude. Comparators are commonly employed as sense amplifiers for static random access memories, dynamic random access memories, as well as on-chip cache memories for microprocessors. Comparators are also commonly employed in buffer circuits that couple an integrated circuit to an external system. Also, comparators are critical elements of analog-to-digital converters and digital-to-analog converters.
A static comparator is a comparator that is always enabled. A static comparator is not timed, controlled, or activated by clock signals. A static comparator is constantly comparing two input voltages. Static comparators may be employed in circuits having no clock signal. Static comparators may also be employed when the input voltages to the comparator change unpredictably, or when the input voltages change at times far removed from a clock edge.
A high speed static comparator implemented on an integrated circuit is typically required to have a short propagation delay between the input and the output of the comparator. A high speed static comparator for an integrated circuit should also have high gain and low power consumption. Moreover, a high speed static comparator should detect differences between two input voltages even when the difference between the input voltages is very slight.
The requirements of high gain and low power consumption are interrelated by a gain bandwidth product (GBW). A static comparator implemented on an integrated circuit is typically modeled as a single pole system having a constant gain bandwidth product. If the gain of the comparator is increased, the bandwidth of the comparator must necessarily decrease. Moreover, the propagation delay of a comparator is inversely proportional to the bandwidth of the comparator. Thus, a static comparator having high gain will necessarily have small bandwidth and a large propagation delay between the input and the output.
FIG. 1 illustrates a typical prior static comparator 100 for an integrated circuit. The static comparator 100 is comprised of a differential amplifier and a current mirror load. The differential amplifier is comprised of a pair of NMOS transistors Q1 and Q2. The current mirror load is comprised of a pair of PMOS transistors Q3 and Q4. A bias current generator 16 generates a bias current (I.sub.BIAS) for the transistors Q1 and Q2.
In an alternative implementation, the transistors Q1 and Q2 are PMOS transistors, and the transistors Q3 and Q4 are NMOS transistors. Also, the static comparator 100 could be implemented with a differential amplifier comprising a pair of NPN bi-polar transistors.
The static comparator 100 senses input voltages at an input node 10 and an input node 12. If the voltage at the input node 10 is greater than the voltage at the input node 12, a current through the transistor Q1 (I.sub.1) is greater than a current through the transistor Q2 (I.sub.2). The current mirror of the static comparator 100 (transistors Q3 and Q4) forces the current difference (I.sub.1 -I.sub.2) to an external circuit coupled to an output node 14.
Typically, the output node 14 is coupled to the gates of the input transistors forming a next circuit stage. The input gates of the next circuit stage provide a capacitance load to the static comparator 100. The current supplied by the static comparator 100 at the output node 14 (I.sub.1 -I.sub.2) charges and discharges the capacitance load provided by the next circuit stage.
The static comparator 100 is slow because a relatively small bias current I.sub.BIAS charges and discharges a capacitance load through a relatively large voltage swing at the output node 14. The voltage swing at the output node 14 is relatively large because the static comparator 100 typically has a relatively large gain. The voltage swing at the output node 14 typically varies between a high level substantially equal to the supply voltage VDD, and a low level substantially equal to the voltage at a tail node 18.
The bias current I.sub.BIAS is typically limited to relatively low levels to maintain low power consumption for the static comparator 100. The propagation delay (.increment.t) for the static comparator is relatively large because the voltage swing at the output node 14 (.increment.v) is relatively large. The propagation delay .increment.t is determined by the following equation which governs the charging and discharging of a capacitance load at the output node 14: I=C.times..increment.v/.increment.t.
The propagation delay .increment.t of the static comparator 100 can be reduced by increasing the bias current I.sub.BIAS. However, the increased bias current I.sub.BIAS causes a corresponding increase in power consumption of the static comparator 100. Unfortunately, the increased power consumption in a static comparator 100 contributes to overall power consumption in a system. In a typical application, an integrated circuit contains many such static comparators. The excessive power consumption of a single static comparator is multiplied across the integrated circuit, thereby causing unacceptably high power consumption for the system.